A bit slice system provides a designer with the tools to customize a processor to the needs of a given application. The bit slice architecture utilizes a bit slice processor which is comprised of a microsequencer and an expanded bit slice arithmetic logic unit (ALU). The microsequencer is combined with a microprogram memory and a microinstruction register to provide control codes for the bit slice ALU. This type of a processor is effectively a computer for disposal within a more sophisticated computer architecture. With the bit slice system, the designer can define the details of the system operation, including the instruction set to be implemented. This allows the designer to deviate from the preset instruction set which is common to most processors.
The bit slice ALU is a fundamental part of the system. This element is designed so that it can be connected to similar elements to provide an ALU of any desired word width. Central to the ALU slice is that its operation can be expanded to any number of bits by interconnection of like ALUs. For example, if an ALU with eight bits per circuit is utilized, four circuits would form the ALU for a thirty-two bit processor. The carry and shift lines provide communication between ALUs so that multiple bit arithmetic operations can be performed.
To provide localized storage for input and output operands, a register file is provided on the bit slice ALU. This register file allows the processing portion of the bit slice ALU to process a number of prestored operands and either output the resultant operand or store the result back in the register file. In order to increase speed, it is necessary to buffer data being extracted from the register file in order to both read data from the register file and write data back to it. Typically, this requires either an additional instruction cycle or separate latches and a multiplexed addressing scheme. Present systems provide only two address inputs to constitute a two operand machine which can be configured to a three operation machine with some multiplexers on the input address lines to allow writing back to a third location.
Register files on present systems have some disadvantages in that they are difficult to design around. This is due to the fact that these systems require external timing controls that must be accounted for in the initial timing design to ensure proper data flow. This significantly increases the design time when implementing a particular bit slice ALU into a bit slice processor. In view of these disadvantages, there exists a need for a bit slice ALU with a register file that is more versatile and tolerant with respect to timing constraints placed upon initial design of the system.